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DC Compact Model for SOI Tunnel Field-Effect Transistors

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3 Author(s)
Bhushan, B. ; Chief Technol. Officer''s Group, Silicon Syst. Group, Singapore, Singapore ; Nayak, K. ; Rao, V.R.

A physics-based dc compact model for SOI tunnel field-effect transistors (TFETs) has been developed in this paper utilizing Landauer approach. The important transistor electrical parameters, i.e., threshold voltage Vth, charge in the channel Q, gate capacitance CG, drain current IDS, subthreshold swing S, transconductance gm, and output conductance gDS, have been modeled. The model predicts the low subthreshold swing values (less than 60 mV/dec) observed in TFETs and shows a good match with the technology computer aided design (TCAD) results. Model validation was carried out using TCAD simulation for different TFET structures with abrupt junctions, i.e., 40-nm Si nTFET and pTFET, a 0.4-μm Si nTFET, and a 40-nm Ge nTFET. The compact model predictions are in good agreement with the TCAD simulation results.

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Electron Devices, IEEE Transactions on  (Volume:59 ,  Issue: 10 )