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Annealing process and structural considerations in controlling extrusion-type defects Cu TSV

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12 Author(s)
Jinho An ; Semicond. R & D Center, Samsung Electron. Co. Ltd., Hwasung, South Korea ; Kwang-Jin Moon ; Soyoung Lee ; Do-Sun Lee
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Stresses induced by the large volume of Cu in Through Silicon Vias (TSV) can result in global/local Cu extrusion which may affect reliability in 3D chip stacking technologies beyond the 28 nm node for high performance mobile devices. In this work, TSV structural factors that can influence extrusion post via filling are studied. In addition, the impact of the electroplating chemistry and annealing schemes on local extrusion type defect formation in TSVs are also studied.

Published in:

Interconnect Technology Conference (IITC), 2012 IEEE International

Date of Conference:

4-6 June 2012