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Design and process development of a stacked SRAM memory chip module with TSV interconnection

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11 Author(s)
Shenglin Ma ; Nat. Key Lab. of Sci. & Technol. on Micro/Nano Fabrication, Peking Univ., Beijing, China ; Xin Sun ; Yunhui Zhu ; Zhiyuan Zhu
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In this paper, a stacked SRAM chip module is presented and simulation results are demonstrated. A novel 3D integration process is presented and challenging issues are addressed. With this novel process, there's no need to do grinding/polishing of copper overburden after filling of TSV by copper electroplating. Copper microbumps will be formed directly on the active side in the filling of TSV by copper electroplating while the ones on the backside will be formed with backside releasing process. A test run is carried out with this novel process and a 4-layer stacked chip module is successfully fabricated.

Published in:

Electronic Components and Technology Conference (ECTC), 2012 IEEE 62nd

Date of Conference:

May 29 2012-June 1 2012