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Development of damage-less wet-chemical silicon-wafer thinning process for three-dimensional integration

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4 Author(s)
Watanabe, N. ; Nanoelectron. Res. Inst., Nat. Inst. of Adv. Ind. Sci. & Technol. (AIST), Tsukuba, Japan ; Miyazaki, T. ; Aoyagi, M. ; Yoshikawa, K.

We evaluated the damage of an etched silicon surface after the wet-chemical silicon-wafer thinning process. The damage evaluation was carried out by cross-sectional transmission electron microscope (TEM) observation/electron energy-loss spectroscopy (EELS) analysis of the etched surface and measurement of die fracture stress. The results of the TEM observation/EELS analysis indicated the absence of damage layers. The three-point bending test showed that this process offered a higher die fracture stress than other processes including backgrinding. We also applied this process to thinning of the CMOS wafer and measured the change in the MOSFET characteristics. The change in MOSFET characteristics was found to be very small even when the CMOS wafer was thinned to 50 μm.

Published in:

Electronic Components and Technology Conference (ECTC), 2012 IEEE 62nd

Date of Conference:

May 29 2012-June 1 2012