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We report new developments on hybrid integration that attaches CMOS driver circuits to silicon photonic (SiPhotonic) devices built in Silicon on Insulator (SOI) technology. This low-parasitic hybrid integration approach enables energy efficient links based on aggressive silicon photonic devices and low power, high speed circuits. The silicon photonic components are fabricated in the 130 nm Cu node of Freescale's SOI-CMOS technology while the CMOS driver circuits are fabricated in 40 nm TSMC ELK technology. The two types of chips are using 20 μm diameter solder bumps. We further present progress on scaling these solder bumps to 10 micron diameter and below as well as developing a wafer scale microsolder process module. Finally, we report progress integrating hybrids that include SOI chips with a partially removed backside. Under full SOI handler removal this bonding geometry is akin to the extreme limit of wafer thinning used in today's vertical chip stacking (3D) approaches.