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Stacking die technology using through-silicon-via (TSV) technology has attracted a lot of attention due to various advantages in performance and integration. However, a high temperature environment during the fabrication process of TSV leads to uncontrollable thermal expansion, which then causes a serious reliability problem, the thermal mechanical problem. This problem can result in deformation or mechanical damage to the dies; therefore, it must be resolved. Unlike previous works applying novel components which are not in the standard CMOS process and thus potentially very expensive, this paper proposes to use package process compatible component, micro bumps, to relax the thermal mechanical stress. In addition, we present an efficient algorithm to place micro bumps in appropriate positions to minimize the total number of micro bumps needed. Our simulated results show that significant reduction on the maximum stress can be achieved. Not only the proposed design can lower the maximum temperature of the hotspot, but improve the thermal uniformity of the test chip. Finally, the infrared radiation thermal images are employed for monitoring the temperature of the virtual cores and that of the hybrid thermal solution. The experimental results show that one of proposed design provides excellent capability for enhancement of thermal conduction.
Date of Conference: May 29 2012-June 1 2012