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The traditional wafer level packages (WLPs) are fan-in redistribution layer (RDL) lay-out design; it may not be able to meet the high pin-count handheld device requirement. So the new fan-out wafer level packages (FOWLPs) are emerged in the last few years. The fan-out WLP starts with the reconfiguration dies on carrier and embeds die by molded compound. The molded reconstituted wafer forms a compound base to apply litho and metallization process, as in the conventional fan-in WLP back-end processes to form the packages. In this study, a new high-performance fan-out wafer level package (sWLP) is developed. Emphasis is placed on the fabrication process and material selection. Since FOWLP with molding process has warpage challenge, herein we use lamination process with dry film to embed dies and adhere with Si wafer on the backside to achieve a ultra low warpage. Also, package level and board level performance are determined by finite element analysis. Furthermore, package and board level reliability are estimated by the standard JEDEC standard. The package warpage behavior corresponding to temperature conditions is measured by moiré method. Some important results for the new package are summarized as below: Assembly process evaluation and improvement; Board level drop test performance and stress/warpage simulation; Shadow moiré measurement and thermal effect study; Reliability results of package level, including precondition, TCT, HTS and HAST; and Reliability results of board level, including drop test and TCT.