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Wafer Level Packaging (WLP) has started to shine and played a prominent role in recent years in both semiconductor and Integrated Circuit (IC) field, especially in now thriving Micro-Electro-Mechanical System (MEMS) applications on account of its distinctive operating mechanism and adaptive design variety. In this study, several crucial WLP technologies are disclosed in detail, including Wafer to Wafer (W2W) bonding, wafer level wire bonding, wafer level compound molding and lapping. Simplified and conceptual process flow of MEMS WLP and development approaches are introduced and explained. Furthermore, relevant experimental results and technology characteristics, including glass frit printing and bonding results & shear strength in W2W bonding technology, wire shift & vertical loop height & ball shear & wire pull in wafer level wire bonding technology, Thickness to Thickness Variation (TTV) & wire sweep & warpage in wafer level compound molding technology, have also been extensively demonstrated. After MEMS WLP packaging process, device performance is then determined by the difference of voltage readout with the implementation of Wafer Level Dynamic Test (WLDT) before and after Highly Accelerated Stress Test (HAST), and the wafer device yield is also presented.