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Novel sidewall interconnection using perpendicular circuit die with non-solder bumps for 3D chip stack

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4 Author(s)
Sun-Rak Kim ; Dept. of Mech. Eng., KAIST, Daejeon, South Korea ; Il Kim ; Jae Hak Lee ; Lee, S.S.

A new sidewall interconnection using perpendicular circuit die is implemented in this work; this device can be applied to fabrication of chip stacks. Experiments were conducted by stacking four chips each having a thickness of 200μm; the configuration of the pad on the test chip is similar to that of a memory chip. The chips for stacking were fabricated successfully by dicing the wafer. Vertical interconnection was made by thermo-compression bonding using a perpendicular circuit die. The interconnection quality of the chip stack was examined through SEM images. The images show that the interconnections were made successfully. A high-temperature/high-humidity test was conducted on the stacked chip. A high-temperature/high-humidity test at 85°/85%RH lasting 1000 hours was used to investigate the mechanical reliability of the packages. It was found that the stacked chips maintained their mechanical integrity. The bonding strength at all of the interfaces remained as high as they were before the test. The electrical resistance of the interconnection is comparable to that obtained using the wire bonding.

Published in:

Electronic Components and Technology Conference (ECTC), 2012 IEEE 62nd

Date of Conference:

May 29 2012-June 1 2012