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3D multi-stacking of thin dies based on TSV and micro-inserts interconnections

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11 Author(s)

This paper is dedicated to the full development of several technological modules mandatory for 3-D multiple die stacking. This includes technologies such as thinning, Through Silicon Vias (TSV) and dies interconnection. A via last approach was chosen to be compatible with die integration coming from various foundries where design, die thickness and contact pad metallurgy are predefined. The interconnection between each die is based on chip on wafer bonding and micro-inserts technology. Small spikes of Ni are formed at the interconnection point between the two circuits. The approach allows a very narrow connection (less than 10 μm of interface) and do not necessitate an underfill. A test vehicle which allows characterizing the required technologies has been designed and manufactured. It consists of 50 μm thick dies including TSV and contact lines on both sides. These dies are stacked on silicon interconnection network enabling to extract electrical signal. The electrical continuity through the stacking was tested from the substrate thanks to Daisy Chain. Finally, these technologies were implemented in a SimCard prototype. The test vehicle and final prototype will be fully described in this paper. A technical focus will be done on the most important process steps for the 3D integration which include vias last integration, micro-bumping and thin die stacking. Several electrical Kelvin structures were measured from the substrate to estimate the contact resistance through micro-inserts and TSV and results will be presented and commented.

Published in:

Electronic Components and Technology Conference (ECTC), 2012 IEEE 62nd

Date of Conference:

May 29 2012-June 1 2012