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Process modeling of dry etching for the 3D-integration with tapered TSVs

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4 Author(s)
Martin Wilke ; Fraunhofer Institut für Zuverlässigkeit und Mikrointegration, Gustav-Meyer-Allee 25, 13355 Berlin, Germany ; Michael Töpper ; Hue Quoc Huynh ; Klaus Dieter Lang

One of the key technologies for 3D packaging is forming the Through Silicon Vias (TSV) using plasma etching. For the 3D packaging of active devices such as CMOS sensors, which exhibit low to moderate I/O counts, it was shown in recent years, that costs for TSV interconnects can be reduced by producing tapered via features, which ease subsequent process steps such as deposition of dielectrics, metal layers and photo resists. For different applications the adjustment of dedicated via profiles is desirable. For the practical use the process engineer is confronted with a variety of different process parameters, which exhibit strong interactions between each other and therefore make an extensive testing necessary when a new process needs to be developed. The knowledge of these interactions is therefore needed. The etching of tapered TSVs using fluorine based chemistry is discussed in this paper. The influence of the governing process parameters such as pressure, gas flow ratio and power is discussed in order to produce profiles with continuous tangent and minimal surface roughness of the structures. Emerging structures with etching effects such as micro masking or the appearance of profiles with gradient taper are shown in order to reveal guidelines in which direction the process needs to be adjusted to stay in the process window. A model is presented and discussed which is able to predict the profile angle as a function of the process parameters. This gives the ability to produce tapered profiles from 65° to 85° without the burden of an enormous experimental effort. Interrelated etching performance such as photoresist selectivity, etching rate and the occurrence of lateral under etching is presented as well so that design rules can be derived for the specific process.

Published in:

2012 IEEE 62nd Electronic Components and Technology Conference

Date of Conference:

May 29 2012-June 1 2012