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To analyze the effects of the on-chip decoupling capacitors (on-chip decaps) and silicon substrate on three-dimensional (3D) stacked on-chip power distribution networks (PDNs) in through silicon via (TSV)-based 3D-ICs, we propose a model for 3D stacked on-chip PDNs that includes the effects of the on-chip decaps and silicon substrate. The model is the RLGC-lumped model based on the segmentation method and scalable equations derived from physical configurations. The model is successfully validated by the 3D EM simulation using CST MWS up to 20 GHz. Using the proposed model, we analyze the effects of the on-chip decaps and silicon substrate on the impedance of 3D stacked on-chip PDNs with respect to variations in the capacitance and position of on-chip decaps, the conductivity of the silicon substrate, and the height between the on-chip PDN and silicon substrate.