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Silicon Interposer with Through Silicon Via (TSV) is a newly developed technology that enables multichip integration and offers great potential to improve system performance with less delay, higher wiring density, and lower power consumption. One challenge of this new technology is to maintain the PDN electrical performance. Micro bumps, TSV, interposer front and back side Re-Distribution Layer (RDL) metallization add additional interfaces and drives up complexity for an optimized PDN design in 3D IC integration. This paper reports on a R&D test vehicle that was developed for engineering evaluation of electrical and physical interfaces through TSV silicon interposer. The test vehicle consisted of a FPGA die side-by-side with its daughter die on a passive silicon interpose. The paper reports TSV loss mechanisms and its performance impacts on Power Delivery Network (PDN). Embedded MIM capacitor is implemented to increase interposer decoupling capacitance (IDC) to improve high speed PDN performance. PDN impedance characteristics are analyzed and evaluated for the interposer-based 3D system combining on-die PDN, interposer power/ground grids, TSV and package/PCB PDN components.