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Evaluation of 3D interconnect routing and stacking strategy to optimize high speed signal transmission for memory on logic

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11 Author(s)
Roullard, J. ; IMEP-LAHC, Univ. de Savoie, Le Bourget du Lac, France ; Farcy, A. ; Capraro, S. ; Lacrevaz, T.
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3D stacking technologies are electrically studied to predict high speed data transmission for memory on logic applications. Maximal frequency of bandwidth for memory-processor and processor-BGA channels are extracted and compared for Face to Face and Face to Back 3D stacking and between an interposer technology. Using expected electrical specifications of Wide IO applications in terms of data rates, a roadmap is proposed in accordance to the integration density, carried out by the TSV density.

Published in:

Electronic Components and Technology Conference (ECTC), 2012 IEEE 62nd

Date of Conference:

May 29 2012-June 1 2012