Referenced Items are not available for this document.
3D stacking technologies are electrically studied to predict high speed data transmission for memory on logic applications. Maximal frequency of bandwidth for memory-processor and processor-BGA channels are extracted and compared for Face to Face and Face to Back 3D stacking and between an interposer technology. Using expected electrical specifications of Wide IO applications in terms of data rates, a roadmap is proposed in accordance to the integration density, carried out by the TSV density.
Published in:
Electronic Components and Technology Conference (ECTC), 2012 IEEE 62nd
Date of Conference: May 29 2012-June 1 2012
- Page(s):
- 8 - 13
- ISSN :
- 0569-5503
- E-ISBN :
- 978-1-4673-1964-5
- Print ISBN:
- 978-1-4673-1966-9
- INSPEC Accession Number:
- 12906887
- Conference Location :
- San Diego, CA
- Digital Object Identifier :
- 10.1109/ECTC.2012.6248798
- Product Type:
- Conference Publications
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