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Structural design, process, and reliability of a wafer-level 3D integration scheme with Cu TSVs based on micro-bump/adhesive hybrid wafer bonding

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14 Author(s)
C. T. Ko ; Electronics and Optoelectronics Research Laboratories, Industrial Technology Research Institute (ITRI), Hsinchu, Taiwan ; Z. C. Hsiao ; Y. J. Chang ; P. S. Chen
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In this study, a wafer-level 3D integration scheme with Cu TSVs based on Cu/Sn micro-bump and BCB adhesive hybrid bonding is demonstrated. To realize the signal transmission effects in high speed digital signaling via Cu TSV and Cu/Sn micro-joint interconnection, the insertion loss was investigated by simulation analysis with variable TSV pitches, micro-bump diameters and chip thicknesses. Key technologies include TSV fabrication, micro-bumping, hybrid scheme making, hybrid bonding, wafer thinning and backside RDL formation were well developed and integrated to perform the 3D integration scheme. 5μm TSV, 10μm micro-bump, 20μm pitch, 40μm thin wafer, and 250°C low temperature W2W hybrid bonding have been successfully integrated in the integration platform. The 3D scheme was characterized and assessed to have excellent electrical performance and reliability, and is potentially to be applied for 3D product applications.

Published in:

2012 IEEE 62nd Electronic Components and Technology Conference

Date of Conference:

May 29 2012-June 1 2012