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In modern CMOS processes, soft errors and metastability are two prominent failure mechanisms. Radiation induced single event upsets, or soft-errors, have become a dominant failure mechanism in sub-100 nm CMOS memory and logic circuits. The effects of metastability have also becoming increasingly significant in high-speed applications implemented in nanometric processes. In this paper the design trade-offs for flip-flops between performance, soft-error robustness and metastability are described. Soft-error robust flip-flops are implemented based on both the DICE cell and the Quatro cell. SPICE simulations are used to characterize the transient performance and metastability robustness, and device level simulations were performed to quantify the soft-error robustness. The flip-flops were fabricated in the TSMC 40 nm process and radiation measurements were performed at several test facilities. The Quatro flip-flop showed improved soft-error robustness and metastability when compared with a reference D flip-flop and a DICE flip-flop.