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A Method to Prevent Strong Snapback in LDNMOS for ESD Protection

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3 Author(s)
Hang Fan ; Sch. of Microelectron. & Solid-States Electron., Univ. of Electron. Sci. & Technol. of China, Chengdu, China ; Lingli Jiang ; Bo Zhang

High injection electron current in an LDNMOS can lead to a strong snapback and latch-up-like characteristic. It is susceptible to latch-up-like in high-voltage ICs, if its holding voltage is lower than the power supply voltage. A method to raise the LDNMOS holding voltage is proposed and verified in a 0.35-μm 20-V/5-V BCD process without additional masks. It is realized by adding a relative high doping Nw provided for a 5-V PMOS in the drain region. The doping concentration in the Nw is higher than the injection electron density from the source under ESD stress. The Nw can extend the length of the space-charge region and lead to a higher voltage drop and high strong snapback current. This way, we get an LDNMOS with holding voltage higher than 24 V.

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Device and Materials Reliability, IEEE Transactions on  (Volume:13 ,  Issue: 1 )