Threshold voltage modeling under size quantization for ultra-thin silicon double-gate metal-oxide-semiconductor field-effect transistor

We report on the threshold voltage modeling of ultra-thin (1 nm–5 nm) silicon body double-gate (DG) MOSFETs using self-consistent Poisson-Schrodinger solver (SCHRED). We define the threshold voltage (V_th) of symmetric DG MOSFETs as the gate voltage at which the center potential (Φ_c) saturates to Φ_c(sat), and analyze the effects of oxide thickness (t_ox) and substrate doping (N_A) variations on V_th. The validity of this definition is demonstrated by comparing the results with the charge transition (from weak to strong inversion) based model using SCHRED simulations. In addition, it is also shown that the proposed V_th definition, electrically corresponds to a condition where the inversion layer capacitance (C_inv) is equal to the oxide capacitance (C_ox) across a wide-range of substrate doping densities. A capacitance based analytical model based on the criteria C_inv=C_ox is proposed to compute Φ_c(sat), while accounting for band-gap widening. This is validated through comparisons with the Poisson-Schrodinger solution. Further, we show that at the threshold voltage condition, the electron distribution (n(x)) along the depth (“x”) of the silicon film makes a transition from a strong single peak at the center of the silicon film to th- onset of a symmetric double-peak away from the center of the silicon film.