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On acceleration of the check tautology logic synthesis algorithm using an FPGA-based reconfigurable coprocessor

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2 Author(s)
J. Cong ; Dept. of Comput. Sci., California Univ., Los Angeles, CA, USA ; J. Peck

We summarize our study on implementing tautology checking, a fundamental logic synthesis algorithm, using an FPGA based reconfigurable application specific coprocessor. The use of the tautology checking algorithm is first discussed followed by the specifics of hardware accelerator implementation and interface to application software. We compare our hardware accelerator for the tautology check algorithm with the software implementation of the tautology check algorithm in Espresso II (R. Rudell and A. Sangiovanni-Vincentelli, 1987). Our experimental results show that our accelerator is capable of achieving a maximum speedup factor of 2.94 and averaging 1.36 on 110 modified industry benchmarks included with the Espresso II package

Published in:

Field-Programmable Custom Computing Machines, 1997. Proceedings., The 5th Annual IEEE Symposium on

Date of Conference:

16-18 Apr 1997