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Implementation of single precision floating point square root on FPGAs

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2 Author(s)
Yamin Li ; Comput. Archit. Lab., Univ. of Aizu, Aizu-Wakamatsu, Japan ; Wanming Chu

The square root operation is hard to implement on FPGAs because of the complexity of the algorithms. In this paper, we present a non-restoring square root algorithm and two very simple single precision floating point square root implementations based on the algorithm on FPGAs. One is low-cost iterative implementation that uses a traditional adder/subtracter. The operation latency is 25 clock cycles and the issue rate is 24 clock cycles. The other is high-throughput pipelined implementation that uses multiple adder/subtracters. The operation latency is 15 clock cycles and the issue rate is one clock cycle. It means that the pipelined implementation is capable of accepting a square root instruction on every clock cycle

Published in:

Field-Programmable Custom Computing Machines, 1997. Proceedings., The 5th Annual IEEE Symposium on

Date of Conference:

16-18 Apr 1997