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A series combining transformer(SCT)-based, watt-level 1.9 GHz linear CMOS power amplifier with an on-chip linearizer is demonstrated. Proposed compact, predistortion-based linearizer is embedded in the two-stage PA to compensate AM-PM distortion of the cascode power stages, and improve ACLR of 3GPP WCDMA uplink signal by 2.6 dB at 28.0 dBm output power. The designed interstage power distributor with one tuning inductor contributes to low-loss power supply for the driver stage and high common-mode stability of the whole PA. Moreover, a newly developed PVT variation- tolerant cascode biasing circuit guarantees highly accurate bias voltages in a wide supply voltage range from 2.5 V to 3.6 V. The test chip demonstrates maximum output power of 28.3 dBm at 1.95 GHz, satisfying 3GPP WCDMA spectrum mask with die area of 5.4 mm2.
Date of Publication: Aug. 2012