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A 16-Gb/s Backplane Transceiver With 12-Tap Current Integrating DFE and Dynamic Adaptation of Voltage Offset and Timing Drifts in 45-nm SOI CMOS Technology

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17 Author(s)
Gangasani, G.R. ; Syst. & Technol. Group, IBM, Hopewell Junction, NY, USA ; Chun-Ming Hsu ; Bulzacchelli, J.F. ; Rylov, S.
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This paper presents a 16-Gb/s 45-nm SOI CMOS transceiver for multi-standard backplane applications. The receiver uses a 12-tap DFE with circuit refinements for supporting higher data rates. Both the receiver and the transmitter use dynamic adaptation to combat parameter drift due to changing supply voltage and temperature. A 3-tap FFE is included in the source-series-terminated driver. The combination of DFE and FFE permits error-free NRZ signaling at 16 Gb/s over channels exceeding 30 dB loss. The 8-port core with two PLLs is fully characterized for 16 GFC and consumes 385 m W/link.

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Solid-State Circuits, IEEE Journal of  (Volume:47 ,  Issue: 8 )