By Topic

Constrained Interleaving of Turbo Product Codes

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

4 Author(s)
Fonseka, J.P. ; Dept. of Electr. Eng., Univ. of Texas at Dallas, Richardson, TX, USA ; Dowling, E.M. ; Brown, T.K. ; Sang Ik Han

Constrained interleaving is presented to improve the performance of turbo product codes. Traditional row/column interleaving achieves the highest possible minimum distance while ignoring the error coefficients, whereas uniform interleaving focuses on reducing the error coefficients while ignoring the minimum distance. Constrained interleaving achieves the highest possible minimum distance thereby forcing error coefficients of all contributions below the highest achievable minimum distance to zero while simultaneously lowering the error coefficients of the remaining contributions close to those of uniform interleaving. We present a lower bound for the error rate with constrained interleaving, and demonstrate using 2D and 3D SPC codes that the bound can be approached reasonably well with a constrained interleaver that is only 2 to 3 times the size of a row/column interleaver. Constrained interleaving performs better than row/column interleaving and the improvement becomes more significant with increasing order of SPC. While uniform interleaving typically uses large interleaver sizes and creates an undesirable error floor, constrained interleaving performs better at much shorter interleaver sizes and eliminates the error floor.

Published in:

Communications Letters, IEEE  (Volume:16 ,  Issue: 9 )