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An Asynchronous Divider Implementation

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2 Author(s)
Jamadagni, N. ; Maseeh Coll. of Comput. Sci. & Eng., Portland State Univ., Portland, OR, USA ; Ebergen, J.

We present an asynchronous implementation of a novel division algorithm previously patented. Our implementation exploits the average-case behavior of the algorithm and uses the versatility of GasP circuits to implement the data-dependent latencies in the algorithm. On average, the delay per quotient bit for our implementation is 6.3 FO4 gate delays compared to 9.5 FO4 gate delays for a similar SRT divider implementation.

Published in:

Asynchronous Circuits and Systems (ASYNC), 2012 18th IEEE International Symposium on

Date of Conference:

7-9 May 2012