Referenced Items are not available for this document.
A high resolution time-to-digital converter (TDC) architecture is proposed. The architecture combines the principles of noise-shaping quantization and charge-pump to build a third-order ΔΣ TDC with a dedicated feedback DAC. Fabricated in a 0.13μm CMOS process, the prototype TDC achieves better than 71dB DR and 67dB SNDR in 2.81MHz signal bandwidth (OSR=16) and consumes 2.58mW.
Published in:
VLSI Circuits (VLSIC), 2012 Symposium on
Date of Conference: 13-15 June 2012
- Page(s):
- 168 - 169
- E-ISBN :
- 978-1-4673-0845-8
- Print ISBN:
- 978-1-4673-0848-9
- INSPEC Accession Number:
- 12881717
- Conference Location :
- Honolulu, HI
- Digital Object Identifier :
- 10.1109/VLSIC.2012.6243843
- Product Type:
- Conference Publications
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