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1.22mW/Gb/s 9.6Gb/s data jitter mixing forwarded-clock receiver robust against power noise with 1.92ns latency mismatch between data and clock in 65nm CMOS

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2 Author(s)
Sang-Hye Chung ; KAIST, Daejeon, South Korea ; Lee-Sup Kim

This paper presents a data jitter mixing forwarded-clock receiver which is robust against power supply induced jitter (PSIJ) and overcomes 1.92ns latency mismatch between data and clock. The forwarded-clock architecture has a tradeoff between the number of clock channels and the achievable data rate due to the lack of the jitter correlation between data and clock. Moreover, PSIJ due to a long clock distribution network and an injection-locked oscillator reduces the jitter correlation further. The proposed receiver eases this tradeoff, and also increases the jitter correlation reduced by PSIJ. The test chip achieves 9.6Gb/s with 1.22mW/Gb/s and occupies only 0.017mm2 in 65nm CMOS.

Published in:

VLSI Circuits (VLSIC), 2012 Symposium on

Date of Conference:

13-15 June 2012