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A 25-Gb/s 2.2-W optical transceiver using an analog FE tolerant to power supply noise and redundant data format conversion in 65-nm CMOS

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11 Author(s)
Takemoto, T. ; Central Res. Lab., Hitachi, Ltd., Kokubunji, Japan ; Yamashita, H. ; Kamimura, T. ; Yuki, F.
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A one-chip transceiver was developed for optical backplanes by integrating an analog FE with data format conversion in 65-nm CMOS. 10×6.25Gb/s electrical signals were converted to 4×25Gb/s optical signals with 25% redundancy to improve resilience against possible LD failure. To alleviate degradation of the optical link due to power-supply variations, a TIA with a noise canceller and a fully differential LDD are proposed. The noise canceller decreases power-supply variations by 98%. Total power consumption was only 2.2W.

Published in:

VLSI Circuits (VLSIC), 2012 Symposium on

Date of Conference:

13-15 June 2012

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