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A 3.14 um2 4T-2MTJ-cell fully parallel TCAM based on nonvolatile logic-in-memory architecture

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8 Author(s)
Matsunaga, S. ; Center for Spintronics Integrated Syst., Tohoku Univ., Sendai, Japan ; Miura, S. ; Honjou, H. ; Kinoshita, K.
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A four-MOS-transistor/two-MTJ-device (4T-2MTJ) cell circuit is proposed and fabricated for a standby-power-free and a high-density fully parallel nonvolatile TCAM. By optimally merging a nonvolatile storage function and a comparison logic function into a TCAM cell circuit with a nonvolatile logic-in-memory structure, the transistor counts required in the cell circuit become minimized. As a result, the cell size becomes 3.14um2 under a 90-nm CMOS and a 100-nm MTJ technologies, which achieves 60% and 86% of area reduction in comparison with that of a 12T-SRAM-based and a 16T-SRAM-based TCAM cell circuit, respectively.

Published in:

VLSI Circuits (VLSIC), 2012 Symposium on

Date of Conference:

13-15 June 2012