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Charge-trap flash memory devices fabricated with nano-scale patterns on the Si3N4 trapping layer

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5 Author(s)
An, Ho-Myoung ; Sch. of Electr. Eng., Korea Univ., Seoul, South Korea ; Kyong Heon Kim ; Kim, H.-D. ; Won-Ju Cho
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We proposed a novel CTF memory structure with surface patterned Si3N4 trap layers, in order to enhance the memory window and the performance for ultra-high density CTF devices. Due to the enlargement of surface memory-trap densities, the CTF devices with nano-scale surface patterns on the Si3N4 trap layer by NSL showed increased memory windows and improved program properties. In addition, the reasonable reliability, including data retention of 10 years and endurance of 104 P/E cycles, was obtained.

Published in:

Silicon Nanoelectronics Workshop (SNW), 2012 IEEE

Date of Conference:

10-11 June 2012

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