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Variation-aware study of BJT-based capacitorless DRAM cell scaling limit

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4 Author(s)
Min Hee Cho ; Dept. of Electr. Eng. & Comput. Sci., Univ. of California, Berkeley, CA, USA ; Wookhyun Kwon ; Nuo Xu ; Liu, T.K.

The scaling limit of the BJT-based capacitorless DRAM cell is investigated via 3-D process and device simulations, accounting for systematic and random sources of variation. The cell design and operating voltages are optimized at each gate length, following a constant electric field methodology. Retention time decreases with gate length, so that the scaling limit is expected to be 16.5 nm or 13 nm, depending on the application.

Published in:

Silicon Nanoelectronics Workshop (SNW), 2012 IEEE

Date of Conference:

10-11 June 2012