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A 12.5-bit 4 MHz 13.8 mW MASH \Delta \Sigma Modulator With Multirated VCO-Based ADC

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5 Author(s)
Zaliasl, S. ; Sch. of Electr. Eng. & Comput. Sci., Oregon State Univ., Corvallis, OR, USA ; Saxena, S. ; Hanumolu, P.K. ; Mayaram, K.
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A novel MASH delta-sigma (ΔΣ) ADC architecture is introduced that has a multirated voltage controlled oscillator (VCO)-based ADC in its second stage. The architecture allows for low power and high speed operation and is insensitive to the VCO linearity. A prototype consists of a first-order switched-capacitor (SC) modulator operating at 100 MHz in the first stage followed by a second-stage VCO-based ADC operating at 1.2 GHz. A custom IC prototype of this architecture achieves 77.3 dB signal-to-noise-ratio (SNR) over a 4 MHz signal bandwidth with a power consumption of 13.8 mW. It was fabricated in a 130 nm 1P8M CMOS process. The resulting FoM is 298 fJ per conversion.

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Circuits and Systems I: Regular Papers, IEEE Transactions on  (Volume:59 ,  Issue: 8 )