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Strain engineered extremely thin SOI (ETSOI) for high-performance CMOS

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36 Author(s)

Khakifirooz, A. ; IBM Res., Albany, NY, USA ; Cheng, K. ; Nagumo, T. ; Loubet, N.
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High-performance strain-engineered ETSOI devices are reported. Three methods to boost the performance, namely contact strain, strained SOI (SSDOI) for NFET, and SiGe-on-insulator (SGOI) for PFET are examined. Significant performance boost is demonstrated with competitive drive currents of 1.65mA/μm and 1.25mA/μm, and I_eff of 0.95mA/μm and 0.70mA/μm at I_off =100nA/μm and V_DD of 1V, for NFET and PFET, respectively.

Published in:
VLSI Technology (VLSIT), 2012 Symposium on

Date of Conference: 12-14 June 2012

Page(s):: 117 - 118
ISSN :: 0743-1562
E-ISBN :: 978-1-4673-0845-8
Print ISBN:: 978-1-4673-0846-5
INSPEC Accession Number:: 12879775

Conference Location :: Honolulu, HI
Digital Object Identifier :: 10.1109/VLSIT.2012.6242489
Product Type:: Conference Publications

Author(s)

Khakifirooz, A.
IBM Res., Albany, NY, USA
Cheng, K. ; Nagumo, T. ; Loubet, N. ; Adam, T. ; Reznicek, A. ; Kuss, J. ; Shahrjerdi, D. ; Sreenivasan, R. ; Ponoth, S. ; He, H. ; Kulkarni, P. ; Liu, Q. ; Hashemi, P. ; Khare, P. ; Luning, S. ; Mehta, S. ; Gimbert, J. ; Zhu, Y. ; Zhu, Z. ; Li, J. ; Madan, A. ; Levin, T. ; Monsieur, F. ; Yamamoto, T. ; Naczas, S. ; Schmitz, S. ; Holmes, S. ; Aulnette, C. ; Daval, N. ; Schwarzenbach, W. ; Nguyen, B.-Y. ; Paruchuri, V. ; Khare, M. ; Shahidi, G. ; Doris, B.

INSPEC: CONTROLLED INDEXING

CMOS integrated circuits

Ge-Si alloys

silicon-on-insulator

INSPEC: NON CONTROLLED INDEXING

ETSOI

NFET

PFET

SiGe

contact strain

engineered extremely thin SOI

high performance CMOS

IEEE TERMS

Epitaxial growth

Logic gates

Performance evaluation

Silicon

Silicon germanium

Strain

Substrates

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