Thermal stress characteristics and impact on device keep-out zone for 3-D ICs containing through-silicon-vias

Thermal stresses in TSV structures have been measured using micro-Raman spectroscopy and precision wafer curvature technique as a function of temperature and during thermal cycling. The results were verified by finite element analysis (FEA) to characterize the thermal stress behavior of the TSV structures. A nonlinear stress relaxation was observed during initial heating and no preferred grain orientation was found, indicating a homogeneous Cu grain structure with no pronounced elastic anisotropy. The stress impact on the keep-out zone (KOZ) for devices near the TSVs was investigated.