By Topic

A highly pitch scalable 3D vertical gate (VG) NAND flash decoded by a novel self-aligned independently controlled double gate (IDG) string select transistor (SSL)

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

11 Author(s)
Chih-Ping Chen ; Emerging Central Lab, Macronix International Co., Ltd., 16 Li-Hsin Road, Hsinchu Science Park, Hsinchu, Taiwan ; Hang-Ting Lue ; Kuo-Pin Chang ; Yi-Hsuan Hsiao
more authors

Despite vertical stacking, the lateral scaling of 3D NAND Flash is critically important because otherwise >;16 stacking layers are needed to be cost competitive to 20nm 2D NAND. In this work, we propose a 3D vertical gate (VG) NAND using a self-aligned independently controlled double gate (IDG) string select transistor (SSL) decoding method. The IDG SSL provides excellent program inhibit and read selection without any penalty of cell size increase, making our 3D VG NAND cell as scalable as conventional 2D NAND. We present the world's first <; 50nm (37.5nm) half-pitch 3D NAND. The BL decoding and page operation methods are illustrated in detail. This highly pitch scalable VG with IDG SSL approach provides a very cost competitive 3D NAND.

Published in:

VLSI Technology (VLSIT), 2012 Symposium on

Date of Conference:

12-14 June 2012