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A 40 nm 144 mW VLSI Processor for Real-Time 60-kWord Continuous Speech Recognition

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8 Author(s)
Guangji He ; Grad. Sch. of Syst. Inf., Kobe Univ., Kobe, Japan ; Sugahara, T. ; Miyamoto, Y. ; Fujinaga, T.
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We have developed a low-power VLSI chip for 60-kWord real-time continuous speech recognition based on a context-dependent hidden Markov model (HMM). Our implementation includes a cache architecture using locality of speech recognition, beam pruning using a dynamic threshold, two-stage language model searching, highly parallel Gaussian mixture model (GMM) computation based on the mixture level, a variable-frame look-ahead scheme, and elastic pipeline operation between the Viterbi transition and GMM processing. The accuracy degradation of the important parameters in Viterbi computation is strictly discussed. Results show that our implementation achieves 95% bandwidth reduction (70.86 MB/s) and 78% required frequency reduction (126.5 MHz) comparing to the referential Julius system. The test chip, fabricated using 40 nm CMOS technology, contains 1.9 M transistors for logic and 7.8 Mbit on-chip memory. It dissipates 144 mW at 126.5 MHz and 1.1 V for 60-kWord real-time continuous speech recognition.

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Circuits and Systems I: Regular Papers, IEEE Transactions on  (Volume:59 ,  Issue: 8 )