Referenced Items are not available for this document.
This paper proposes a new flash time-to-digital converter (TDC) design, which incorporates deterministic, variable delay into the decision elements. These are implemented with cross-coupled NAND standard cells of variable transistor widths. Both experiment and simulation are used to validate this new design, which provides variable time-difference ranges by controlling the input slew rate. It is also possible to use the proposed flash TDC as a soft macro.
Published in:
Radio Frequency Integrated Circuits Symposium (RFIC), 2012 IEEE
Date of Conference: 17-19 June 2012
- Page(s):
- 527 - 530
- ISSN :
- 1529-2517
- E-ISBN :
- 978-1-4673-0415-3
- Print ISBN:
- 978-1-4673-0413-9
- INSPEC Accession Number:
- 12880678
- Conference Location :
- Montreal, QC
- Digital Object Identifier :
- 10.1109/RFIC.2012.6242338
- Product Type:
- Conference Publications
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