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5.8 GHz low-flicker-noise CMOS direct-conversion receiver using deep-n-well vertical-NPN BJT

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6 Author(s)
Yu-Chih Hsiao ; Dept. of Electr. Eng., Nat. Chiao Tung Univ., Hsinchu, Taiwan ; Chinchun Meng ; Jin-Siang Syu ; Chia-Ling Wang
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This paper demonstrates a 5.8 GHz low-power, low-flicker-noise direct-conversion receiver using deep-n-well vertical-NPN BJT based subharmonic Gilbert mixer. The deep-n-well vertical-NPN BJT is placed in the LO switching core of the bottom-level subharmonic mixer and the input transconductance stage of the subsequent IF VGA. As a result, the flicker noise corner is improved and the noise figure is 9.5 dB at IF=100 kHz. The maximum gain reaches 50 dB in the operated frequency. The total power consumption is 10 mW at 1.8 V supply voltage.

Published in:

Radio Frequency Integrated Circuits Symposium (RFIC), 2012 IEEE

Date of Conference:

17-19 June 2012

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