By Topic

A 14.1-GHz dual-modulus prescaler in 130nm CMOS technology using sequential implication logic cells

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

4 Author(s)
Wu-Hsin Chen ; Sch. of Electr. & Comput. Eng., Purdue Univ., West Lafayette, IN, USA ; Roa, E. ; Wing-Fai Loke ; Byunghoo Jung

In this work, we demonstrate the use of a non-traditional logic for the implementation of a dual-modulus prescaler. The proposed prescaler consumes less power than TSPC designs and is faster than ETSPC designs. The maximum speed reaches up to 96% of that of a single divide-by-2 D-flip-flop, the theoretical limit. Implemented in 130-nm CMOS technology, the maximum input frequency reaches 14.1GHz with a power consumption of 1.2mW.

Published in:

Radio Frequency Integrated Circuits Symposium (RFIC), 2012 IEEE

Date of Conference:

17-19 June 2012