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In this work, we demonstrate the use of a non-traditional logic for the implementation of a dual-modulus prescaler. The proposed prescaler consumes less power than TSPC designs and is faster than ETSPC designs. The maximum speed reaches up to 96% of that of a single divide-by-2 D-flip-flop, the theoretical limit. Implemented in 130-nm CMOS technology, the maximum input frequency reaches 14.1GHz with a power consumption of 1.2mW.