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A 21.8–27.5GHz PLL in 32nm SOI using Gm linearization to achieve −130dBc/Hz phase noise at 10MHz offset from a 22GHz carrier

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14 Author(s)
Sadhu, B. ; Univ. of Minnesota, Minneapolis, MN, USA ; Ferriss, M.A. ; Plouchart, J.-O. ; Natarajan, A.S.
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This paper describes a new approach to low phase noise LC VCO design based on transconductance linearization of the active devices. A prototype 25GHz VCO based on this approach is integrated in a dual loop PLL and achieves superior performance compared to the state of the art. The design is implemented in the 32nm SOI deep sub-micron CMOS technology and achieves a phase noise of -130dBc/Hz at 10MHz offset from a 22GHz carrier. Additionally, the paper introduces a new layout approach for switched capacitor arrays that enables a wide tuning range of 23%. More than 500 measurements across PVT variations validate the proposed PLL design: phase noise variation across 46 dies for 3 different frequencies is σ <; 0.6dB, across supply variation over 0.7-1.5V is 2dB and across 80°C temperature variation is 2dB. At the 25GHz center frequency, the VCO FOMT is 188dBc/Hz.

Published in:

Radio Frequency Integrated Circuits Symposium (RFIC), 2012 IEEE

Date of Conference:

17-19 June 2012