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A 1 GHz 1.3 dB NF +13 dBm output P1dB SOI CMOS low noise amplifier for SAW-less receivers

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4 Author(s)
Bum-Kyum Kim ; Dept. of EE, Korea Adv. Inst. of Sci. & Technol., Daejeon, South Korea ; Donggu Im ; Jaeyoung Choi ; Kwyro Lee

A complementary capacitive loaded LNA is implemented for 1 GHz application using a 0.18-μm SOI CMOS process. In order to improve both NF and linearity at the same time, the capacitive loading technique to achieve minimum NF and the complementary superposition with body-bias control to improve linearity are adopted. Owing to the capacitive loading technique, the required inductance of the gate inductor for minimum noise matching can be reduced compared to conventional inductive source-degenerated LNA. In case using on-chip gate inductor to implement fully integrated LNA, this greatly reduces the noise contribution of the gate inductor. The complementary superposition with body-bias control improves large signal linearity of gain compression (P1dB) as well as small signal linearity of third-order intercept point (IP3). The measurements demonstrate that the LNA, which is designed for 50 Ω system, has a power gain of 10.7 dB, a NF of 1.3 dB, an OIP3 of +29.1 dBm, and an output P1dB of +12.7 dBm at 1 GHz while drawing 20 mA from a 2.5 V supply voltage.

Published in:

Radio Frequency Integrated Circuits Symposium (RFIC), 2012 IEEE

Date of Conference:

17-19 June 2012