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Gate oxide reliability improvement for CMOS and MEMS monolithic integration

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11 Author(s)
L. Y. Tsai ; Taiwan Semiconductor Manufacturing Company, 121, Park Ave. 3, Hsinchu Science Park, Taiwan 300 ; P. C. Yeh ; L. -Y. Leu ; X. X. Kuo
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Monolithic integration of 0.18μm 1.8/3.3V CMOS and Micro Electro Mechanical Systems (MEMS) was developed by CMOS first/MEMS last scheme (CMOS-MEMS). During process development, gate oxide reliability is a major concern which can be observed due to (1) electrostatic charge damage through bonding pads during the die sawing stage of MEMS cap formation and (2) plasma induced damage (PID) during MEMS deep via etch and MEMS pattern etching. Electrostatic charge damage can be much improved by reducing the die sawing time, optimizing die saw cleaning recipe, and removing the pad oxide before MEMS cap formation. An electrostatic charge model has been developed to explain the gate oxide reliability characteristics. PID can be minimized through gated diode or P/N junction diode protection to provide another effective approach for electrical shielding of the MEMS device in our prior work [1].

Published in:

Reliability Physics Symposium (IRPS), 2012 IEEE International

Date of Conference:

15-19 April 2012