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Differential thermal expansion mismatch between Cu and Si along with high aspect ratios required for TSV pose unique challenges to the integration and reliability of Cu TSV. A TSV structure that successfully mitigates these concerns has been integrated into CMOS with high K/metal gates. Data from test structures demonstrate no `Cu pumping' or other deleterious effects to neighboring devices or interconnects. Functional 3D prototypes utilizing stacked embedded DRAMs were demonstrated showing no impact from TSV processing.