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Copper through silicon via (TSV) for 3D integration

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16 Author(s)
Kothandaraman, C. ; Semicond. R&D Center (SRDC), IBM, Hopewell Junction, NY, USA ; Himmel, B. ; Safran, J. ; Golz, J.
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Differential thermal expansion mismatch between Cu and Si along with high aspect ratios required for TSV pose unique challenges to the integration and reliability of Cu TSV. A TSV structure that successfully mitigates these concerns has been integrated into CMOS with high K/metal gates. Data from test structures demonstrate no `Cu pumping' or other deleterious effects to neighboring devices or interconnects. Functional 3D prototypes utilizing stacked embedded DRAMs were demonstrated showing no impact from TSV processing.

Published in:

Reliability Physics Symposium (IRPS), 2012 IEEE International

Date of Conference:

15-19 April 2012

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