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Optimizing memory hierarchy allocation with loop transformations for high-level synthesis

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3 Author(s)
Cong, J. ; Comput. Sci. Dept., Univ. of California, Los Angeles, CA, USA ; Peng Zhang ; Yi Zou

For the majority of computation-intensive application systems, off-chip memory bandwidth is a critical bottleneck for both performance and power consumption. The efficient utilization of limited on-chip memory resources plays a vital role in reducing the off-chip memory accesses. This paper presents an efficient approach for optimizing the on-chip memory allocation by loop transformations in the imperfectly nested loops. We analytically model the on-chip buffer size and off-chip bandwidth after affine loop transformation, loop fusion/distribution and code motion. Branch-and-bound and knapsack reuse techniques are proposed to reduce the computation complexity in finding optimal solutions. Experimental results show that our scheme can save 40% of on-chip memory size with the same bandwidth consumption compared to the previous approaches.

Published in:

Design Automation Conference (DAC), 2012 49th ACM/EDAC/IEEE

Date of Conference:

3-7 June 2012