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GDRouter: Interleaved global routing and detailed routing for ultimate routability

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2 Author(s)
Yanheng Zhang ; Placement Technol. Group, Cadence Design Syst., San Jose, CA, USA ; Chu, C.

Improving detailed routing routability is an important objective of a global router. In this paper, we propose GDRouter, an interleaved global routing and detailed routing algorithm for the ultimate routability i.e., detailed routing routability. The newly proposed router makes the global routing aware of detailed routing routability by correctly setting global capacity to reduce the inconsistency between the two stages. The final result contains both the detailed routing guided global routing and deailed routing solutions. Fast and efficient academic global routing and detailed routing tools FastRoute [1] and RegularRoute [2] are interleaved in GDRouter. In the Initial Capacity and Routing Weight Esitmation (ICRWE) phase, the weight for each global and detailed routing grid is calculated to make GDRouter aware of pin distribution based on a Gridded Voronoi Diagram method. Then the algorithm generates initial global capacity based on both local usage and global segment usage. In particular, Spine routing is utilized to estimate local usage. And a virtual routing i.e. fast implementations of FastRoute and RegularRoute, is performed to estimate global segment usage. The initial global capacity is applied in Full Routing phase to obtain detailed routing routability i.e., number of unassigned global segment. To further improve routability, in the following Iterative Test Routing (ITR) phase, GDRouter incrementally applies the interleaved global routing and detailed routing to adjust the global capcity based on detailed routing solution. To save runtime, GDRouter quits the loop if detailed routing routability stops improving or it reaches maximum iteration. Experimental results reveal that the newly proposed algorithm is capable of enhancing detailed routing routability. In particular, GDRouter reduces number of unassigned global segments by 90% for ISPD98 [3] derived testcases and around 60% for ISPD05/06 [4, 5] derived testcases with 2.9× runtime overhead.

Published in:

Design Automation Conference (DAC), 2012 49th ACM/EDAC/IEEE

Date of Conference:

3-7 June 2012

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