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Custom designed CPU architecture based on a hardware scheduler and independent pipeline registers - architecture description

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3 Author(s)
Dodiu, E. ; Stefan cel Mare Univ., Suceava, Romania ; Gaitan, V.G. ; Graur, A.

In order to assure the Quality of service (QoS) for some real time applications software schedulers tend to raise the OS tick frequency. Most of the times this is not a convenient solution because the imposed additional overhead can lead to a task deadline missing plus an application failure. It is possible to minimize this overhead by performing the task context switch operation in a dedicated hardware component. This paper presents a custom designed architecture with multi pipeline registers and a dedicated hardware scheduler meant to improve context switch and scheduler times compared to traditional software schedulers.

Published in:

MIPRO, 2012 Proceedings of the 35th International Convention

Date of Conference:

21-25 May 2012