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High-gain charge pumps use MOS switches to rearrange the topology of the circuit in the adjacent half periods of the clock signals, which enables the charge pump circuit to achieve high output voltage. The MOS switches must be adequately controlled to enable fast charge transfer while turned “on” and to prevent leakage current while in the “off” state. This paper presents the limitations of the Cascode Voltage Switch Logic (CVSL) circuit as a control circuit for MOS switches. The operation of the CVSL driver is discussed and the negative effects of the capacitive load associated with the CVSL output node are analyzed.