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An At-Speed Test Technique for High-Speed High-order Adder by a 6.4-GHz 64-bit Domino Adder Example

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4 Author(s)
Yu-Shun Wang ; Grad. Inst. of Electron. Eng., Nat. Taiwan Univ., Taipei, Taiwan ; Min-Han Hsieh ; Li, J.C.-M. ; Chen, C.C.-P.

This work presents the first case of using the pseudoexhaustive testing (PET) for high-speed high-order (>;32 -bit) adders. It is shown that all single stack-at faults are detected by a pseudoexhaustive test set of 54 K patterns, compared to 264×2 patterns in the past. Also, all transition faults are detected by a pseudoexhaustive test set of 13 M patterns, compared to 264×4 patterns in the past. In addition, with a programmable-delay clock generated from DLL, the adder latency is accurately measured. The proposed technique was validated by an example of a 6.4-GHz domino adder with 181 ps latency in a 90-nm CMOS technology. With the latency measurement, speed binning of high performance CPUs is now possible.

Published in:

Circuits and Systems I: Regular Papers, IEEE Transactions on  (Volume:59 ,  Issue: 8 )

Date of Publication:

Aug. 2012

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