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As one of the most complicated manufacturing processes, semiconductor manufacturing consists of four steps, wafer sort, wafer fabrication, assembly, and testing. Among them, wafer fabrication is the most costly, complex, and time consuming step. Its operation management and optimization are challenging modeling and scheduling researchers. To address its modeling issue, a hierarchical colored timed Petri net (HCTPN) is proposed, which can be used to describe various states, behavior and substructures of a wafer fabrication system. To address its scheduling issue, intelligent algorithms are introduced to the proposed HCTPN. An extended genetic algorithm (EGA) embedded scheduling strategy over HCTPN is studied to optimize the combination of scheduling policies. The combined approach can conduct more efficient search with better scheduling performance. At last, a real case is presented to illustrate the results. Based on comparing simulation results of different scheduling strategies, the HCTPN and EGA combined scheduling is proved to be valid and efficient.