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A highly linear, efficient, two-stage power amplifier for high-data-rate wireless applications is presented. The linearity is greatly improved by adding an auxiliary amplifier to the main bipolar transistor amplifier in a feed-forward approach to cancel out the nonlinearity terms. The efficiency enhancement is achieved using a switchable biasing and a reconfigurable output-matching network based on the available input power which is monitored by an on-chip envelope detector. The PA is fabricated using 0.25- μm SiGe:C BiCMOS technology and works at 2 GHz with a supply voltage of 2.5 V. The experimental results show a gain of 13 dB and a maximum output power of 23 dBm with a PAE of 38%. The 1-dB output power compression point is 21 dBm with a 32% PAE. The 6-dB power back-off PAE is 23%. The IM3 and IM5 terms are 41 and 44 dB below the fundamental tone for the 21-dBm output power, respectively. The EVM has been measured to be -30.7 dB at 15-dBm average output power using IEEE 802.16e standard WiMAX 64QAM modulated signal. By employing the linearization technique, EVM and ACLR are improved by 4.5 and 5 dB, respectively, for a WiMAX 64QAM 10-MHz signal bandwidth at 14-dBm average output power.
Date of Publication: Oct. 2012