By Topic

VHDL models supporting a system-level design process: a RASSP approach

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

3 Author(s)
J. A. DeBardelaben ; Center for Signal & Image Process., Georgia Inst. of Technol., Atlanta, GA, USA ; V. K. Madisetti ; A. J. Gadient

The successful Rapid Prototyping of Application-Specific Signal Processors (RASSP) program of the US Department of Defense (DARPA and Tri-Services) targets a 4× improvement in cost and cycle time for design, prototyping, manufacturing, and support processes (relative to current practice). We describe a RASSP-based virtual prototyping process which incorporates parametric cost modeling into a hardware-less VHDL co-simulation and co-verification environment for rapid prototyping. We demonstrate this VHDL-based approach by applying it to the design of a synthetic aperture radar (SAR) system. We present quantitative estimates of the improvements in prototyping time and cost

Published in:

VHDL International Users' Forum, 1997. Proceedings

Date of Conference:

19-22, Oct 1997